The present invention relates to a semiconductor device and more particularly to a semiconductor device having high integration density, composed of miniaturized elements and operable with batteries or low voltage at high speed.
The density of an LSI (Large Scale Integration) has been increased by miniaturizing MOS transistors as its components. In so-called LSIs with deep sub-micron dimension where the size of the elements is 0.5 microns or less, an increase in the power consumption of the LSIs and a decrease in the breakdown voltage of the elements become an issue. In order to cope with such problem, it is considered to be effective means to reduce the operating voltage of the elements as the elements are miniaturized. Five volts are mainly used as the supply voltage for the current LSIs, so that techniques which mount a voltage down converter which converts an external supply voltage to an internal supply voltage on an LSI chip as means for constituting an LSI with miniaturized elements are described in IEEE Journal of Solid-State Circuits, Vol. 21, No. 5, pp. 605-610, October 1986. In this case, the external and internal supply voltages are 5 and 3.5 volts, respectively. As just described above, the problem of power consumption is being revealed in LSIs, especially in the highest density DRAMs (Dynamic Random Access Memories). There is a move to reduce the external supply voltage for the LSIs in conformity to such tendency. For example, the external power supply for a 64-megabit DRAM using, for example, 0.3-micron patterning technologies is expected to be reduced to about 3.3 volts. As the density of the LSIs increases, the external supply voltage may be further decreased.
Recently, as electronic portable equipment has been used widely, the demand for a low-voltage low-power consumption LSI which is operable with batteries and able to store information with batteries increases. For these applications, an LSI which operates a minimum voltage of 1-1.5 volts is required. Especially, in the case of a dynamic memory, its density has already reached a megabit level. There is also a move to use dynamic memories in the field of large capacity memory systems in which only magnetic disk units could conventionally be used. To this end, it is necessary to back up the dynamic memories with batteries such that no data is lost even if the power source is turned off. Usually, the backup interval requires a few weeks to a few years. Therefore, the power dissipation in the memory is required to be minimized. To achieve low power dissipation, it is effective to reduce the operating voltage. If the operating voltage is reduced to about 1.5 volts, a single dry battery will suffice for the backup power source. The cost and the space which the power source occupies are reduced.
In a CMOS (Complementary MOS) LSI, for example a processor, composed of only inverters and various digital logic circuits, no great decrease in the performance will be invited if device dimensions and gate threshold voltages of the MOS transistors are selected appropriately, even if the power supply voltage is reduced to about 1.5 volts. However, in an LSI which uses an external supply voltage and its intermediate voltages for operating purposes, a definite degradation has been brought about in performance. An DRAM is typical of such LSIs.
The conventional DRAMs, mainly used, have problems with the following three elements in terms of high speed operation and stable operation when operated with low voltage:
(1) An input/output (I/O) control circuit which reads a small signal from a memory cell; PA1 (2) A circuit which generates a high voltage required for word line driving to transmit a signal; and PA1 (3) An intermediate voltage generator. PA1 (a) If I/O control MISFETs (T50, T51) are put in an on-state before enough voltage difference is established between data lines (D0, D0), the operation of an sense amplifier SA0 is disturbed and fails: PA1 (b) For the above reason, a timing margin is required to be set from the time when the sense amplifier is started to the time when the MISFETs are put in the on-state by applying a select signal Y01 to the MISFETs. Therefore, the operating speed is reduced (FIG. 2C). PA1 (c) In order to prevent such operation failure, restrictions in design are imposed on the ratio in channel (or drain-source) conductance of the first-mentioned MISFETs to the MISFETs constituting the sense amplifier. Generally, the former is required to be smaller than the latter. In this case, it is difficult to obtain a large driving capability for the common I/O lines (IO0, IO0). Thus the operating speed is further reduced. PA1 (d) Mainly for the reason of (c), it is difficult to write or read data in parallel between the single common I/O line pair and a plurality of data lines connected to the common I/O line pair. Therefore, the parallel testing scheme by selecting multiple I/O gates cannot be applied to the conventional system.
These circuits of the prior art will be described in order.
Concerning (1), as an LSI increases in density and scale, parasitic capacitance on signal lines also increases. Therefore, the operating speed of the LSI decreases. In the case of a dynamic memory, the speed of amplifying a small signal read to a data line from each memory cell using a sense amplifier and the operating speed of an input/output signal line (common I/O line) to read information from a selected data line occupies a large percentage of the operating speed of the entire memory, and techniques for increasing such speeds are indispensable for improving the performance of the memory. A conventional input/output control circuit is described, for example, in IEEE, Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, pp. 663-667. In this article, a system is described which controls the connection of a pair of data line and a pair of common I/O lines by applying a select signal to the gate electrodes of two MISFETs (Metal Insulator Semiconductor Field Effect Transistors). However, this system has the drawback that the propagation delay of a signal is increased under the use of low voltage.
Concerning (2), a conventional example is shown in FIG. 9. This shows a circuit related to a memory cell array (MA) and a word driver (WD) of a DRAM. FIG. 10 shows the waveforms at several elements of the circuit. This circuit is disclosed, for example, in IEEE, Journal of Solid-State Circuits, Vol. SC-21, No. 3, June 1986, pp. 381-389. According to this system, no high voltage is applied to a word line when a low supply voltage is used.
Concerning (3), for example, see IEEE, Journal of Solid-State Circuits, Vol. 21, No. 5, pp. 643-647, October 1986. However, the techniques disclosed this article have the drawback that the driving capability is greatly reduced when a low supply voltage is used.
U.S. application Ser. No. 366,869 filed Jun. 14, 1989 is an earlier application directed also to a low voltage-operated semiconductor device related to the semiconductor memory according to the present invention.